`ifndef __AXI_TYPE_DEF_SVH_INCLUDED
`define __AXI_TYPE_DEF_SVH_INCLUDED

typedef bit [7:0]	uint8_t;
typedef bit [15:0]  uint16_t;
typedef bit [31:0]  uint32_t;
typedef bit [63:0]  uint64_t;

parameter AXI_ADDR_BUS_WIDTH = 32;

parameter AXI_DATA_BUS_WIDTH = 32;


typedef struct packed {
	// write address channel signals #########################################
	reg [3:0]AWID;
	reg [AXI_ADDR_BUS_WIDTH-1:0]AWADDR;
	reg [3:0]AWLEN;
	reg [2:0]AWSIZE;
	reg [1:0]AWBURST;
	reg [1:0]AWLOCK;
	reg [3:0]AWCACHE;
	reg [2:0]AWPROT;
	reg AWVALID;

	// write data channel signals ##############
	reg [3:0]WID;
	reg [AXI_DATA_BUS_WIDTH-1:0]WDATA;
	reg [3:0]WSTRB;
	reg WLAST;
	reg WVALID;

	// write response channel signals ##########
	reg BREADY;

	// read address channel signals ############
reg [3:0]ARID;
	reg [AXI_ADDR_BUS_WIDTH-1:0]ARADDR;
	reg [3:0]ARLEN;
	reg [2:0]ARSIZE;
	reg [1:0]ARBURST;
	reg [1:0]ARLOCK;
	reg [3:0]ARCACHE;
	reg [2:0]ARPROT;
	reg ARVALID;

	// read data channel signals ###############
	reg RREADY;
	//AXI4 ###############
	reg [3:0]AWQOS;
	reg [3:0]ARQOS;
	reg [3:0]AWREGION;
	reg [3:0]ARREGION;
	

} axi_req_t;

typedef struct packed {
	// write address channel signals #########################################
	bit AWREADY; // input
	// write data channel signals ##############
	bit WREADY; // input
	// write response channel signals ##########
	bit [3:0]BID;	// input	 match the AWID
	bit [1:0]BRESP; // input	write response, {OKAY, EXOKAY, ALVERR, DECERR}
	bit BVALID;	  // input	write response valid
	// read address channel signals ############
	bit ARREADY; // input
	// read data channel signals ###############
	bit [3:0]RID; // input
	bit [AXI_DATA_BUS_WIDTH-1:0]RDATA; // input
	bit [1:0]RRESP; // input
	bit RLAST; // input
	bit RVALID; // input

} axi_resp_t;

typedef struct packed{
	bit ACLK;
	bit ARESETn;

	// low-power interface signals #############
	bit AXI_CSYSREQ; // input
	bit AXI_CSYSACK; // input
	bit AXI_CSYSACTIVE; // input

	axi_req_t req;
	axi_resp_t resp;
} axi_t;

/*typedef enum logic [7:0] {AXI_IDLE	= 8'b00000001,
		AXI_R_ADDR_SENT		= 8'b00000010,
		AXI_R_WAIT_DATA		= 8'b00000100,
//		AXI_R_INIT_R		= 8'b00001000,
		AXI_W_WAIT_AWREADY	= 8'b00010000,
		AXI_W_WAIT_DATA		= 8'b00100000,
		AXI_W_WAIT_BVALID	= 8'b01000000,
//		AXI_W_INIT_W		= 8'b10000000,
		AXI_UNKNOWN		= 8'bx
		} cache_axi_state_t;*/
typedef enum reg [2:0] {AXI_IDLE	= 3'h0,
		AXI_R_ADDR_SENT		= 3'h1,
		AXI_R_WAIT_DATA		= 3'h2,
//		AXI_R_INIT_R		= 8'b00001000,
		AXI_W_WAIT_AWREADY	= 3'h3,
		AXI_W_WAIT_DATA		= 3'h4,
		AXI_W_WAIT_BVALID	= 3'h5,
//		AXI_W_INIT_W		= 8'b10000000,
		AXI_UNKNOWN		= 3'h6
		} cache_axi_state_t;

`endif //__AXI_TYPE_DEF_SVH_INCLUDED